RV64GC (C910 cores)
The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months.
I mean things like the Milk-V Pioneer were already faster but expensive.
One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That and US sanctions (eg. Sophgo SG2380).
It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
The idea is to promote testing on RISC-V and to eliminate lack of hardware for being the reason not to. Obviously, low budget projects and Open Source are the primary targets. Commercial products can afford real RISC-V hardware.
This is who you are trusting: https://riseproject.dev/members/
by Ludovic Henry, RISE
Today, we are excited to announce the Early Availability of the RISE RISC-V Runners, a free, managed GitHub Actions runner service that gives any open source project access to real RISC-V hardware in their CI pipelines. No emulation, no cross-compilation hacks, no waitlist. Install a GitHub App, change one line in your workflow, and your jobs run on physical RISC-V boards.
One of the key barriers to RISC-V adoption is the classic chicken-and-egg problem: software projects won’t add RISC-V support without hardware to test on, and hardware adoption slows when the software ecosystem isn’t ready. Emulators like QEMU are invaluable for development, but they can’t catch the real-world issues (performance regressions, architecture-specific compiler bugs, kernel quirks) that only show up on actual silicon.
Until now, most open source projects that wanted to test on RISC-V hardware had to source their own boards, manage their own infrastructure, or rely on limited and oversubscribed shared resources. That’s a lot to ask of a maintainer who just wants to know if their library builds and passes tests on riscv64.
The RISE RISC-V Runners remove that barrier entirely. As part of the RISE Project’s mission to accelerate the RISC-V software ecosystem, we are providing this service free of charge to any open source project on GitHub.
Getting started takes minutes. There are two GitHub Apps depending on where you want to use the runners:
Install the one that fits your setup, then use the `ubuntu-24.04-riscv` label in your workflow:
jobs: build: runs-on: ubuntu-24.04-riscv steps: - uses: actions/checkout@v4 - run: uname -m # prints riscv64
That’s it. Behind the scenes, when your workflow triggers, a webhook is sent to our backend, which provisions a fresh Kubernetes pod on a dedicated RISC-V node. The pod registers as an ephemeral just-in-time GitHub Actions runner, executes your job, and is cleaned up automatically afterward. Every job gets a clean environment, and Docker-in-Docker is available out of the box, so docker build, docker run, Docker Compose, and Buildx all work as expected.
There is no approval process and no allowlist. If your project is on GitHub, you can start using RISC-V runners today.
The runners execute on bare-metal RISC-V servers provided by Scaleway, whose EM-RV1 instances have been central to RISE’s infrastructure efforts. Each node runs at most one job at a time, ensuring consistent and predictable performance for every run.
The entire platform is open source and spans four repositories:
If you maintain an open source project and have ever wondered “does this work on RISC-V?”, this service is for you. Whichever project you maintain, adding a RISC-V CI job is now as simple as adding a new entry to your workflow matrix.
We’ve designed the runner environment to be as close to GitHub’s standard hosted runners as possible, so existing workflows should require minimal changes beyond the runs-on label.
We want the RISC-V software ecosystem to grow, and that starts with making it easy for projects to test on real hardware. Here’s how you can help:
runs-on: ubuntu-24.04-riscv to your CI.Full documentation, including installation instructions, workflow configuration, runner labels, and architecture details, is available at riseproject-dev.github.io/riscv-runner.
We believe that accessible CI infrastructure is one of the important things we can provide to accelerate RISC-V adoption. We look forward to seeing what you build, and what you break, on RISC-V.