The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.
What the project covers:
- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging
- CORDIC for trig functions, verified to 14 significant digits
- Two-pass assembler in Python (~700 lines)
- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware
- Scripting language on top of the microcode for adding functions without touching hardware
- Custom PCB (EasyEDA/JLCPCB), battery, charging circuit
Write-up: https://baltazarstudios.com
Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...
What is the trick to engineering HP calculator keys? Nobody gets keys right like the old HP calculators.
In this age of 3D printing and fast prototypes, we really ought to be able to crack this.
I'm holding in my hand a 4-bit Von Neumann Mostek MK50310N that my father and I used to use to build calculators long ago. Although Mostek made chips for HP (such as the HP-35), they weren't commercially available, but the 50310 was. We could only dream of a project such as yours. I was happy when the "open source" NumWorks was released, but this project aligns more with my interests.
Will definitely install the Qt simulator - would be even better to build one IRL!
"Sure!" (hands over HP-25C)
<start counting seconds...>
"Hey, where's the equals key?"
This project implements a fully functional scientific calculator in hardware using an FPGA. It includes a custom soft CPU, microcode firmware, and supporting tools.
For the full story, see the blog.
Try it in a web browser:

| Folder | Description |
|---|---|
verilog/ |
SystemVerilog source files for the CPU, ALU, I/O, and test benches |
ucode/ |
Microcode (firmware) for the soft CPU |
quartus/ |
Quartus project files for FPGA synthesis |
modelsim/ |
ModelSim simulation setup |
Qt/ |
Qt-based simulator and debugger (uses Verilator) |
calctest/ |
Command-line test harness for hardware verification (uses Verilator) |
tools/ |
Assembler and script compiler for the microcode |
Pathfinding/ |
Algorithm research and verification projects |
The fastest way to try the calculator is to build the Qt simulator:
# From WSL2
cd /mnt/c/Projects/FPGA-Calculator/verilog
make qt
Then open Qt/Calculator.pro in Qt Creator and build for "Desktop Qt MSVC2022 64 Bit".
See the verilog/ and Qt/ folders for detailed instructions.
Install these tools depending on your target:
| Tool | Purpose | Notes |
|---|---|---|
| Verilator | Verilog simulation | Required for Qt simulator |
| Qt | Desktop/WebAssembly/Android app | Version 6.9+ |
| Quartus | FPGA synthesis | Version 13.0 SP1 for Cyclone II |
| ModelSim | Waveform simulation | Optional |
| Visual Studio 2022 | C++ compiler for Qt | Community Edition |
| Python 3 | Assembler and tools |
Verilator runs in WSL2 (Windows Subsystem for Linux). The project source files reside on a Windows partition and are accessed from WSL2.
| Target | Verilator Version | Notes |
|---|---|---|
| Desktop (Qt/MSVC) | 5.x (latest) | Recommended |
| WebAssembly | 4.228 | Required (no thread support) |
# Install prerequisites
sudo apt-get install build-essential autoconf flex libfl-dev bison
# Clone and build Verilator
git clone https://github.com/verilator/verilator
cd verilator
git checkout v5.042 # For Desktop, or v4.228 for WebAssembly
autoconf
./configure
make -j8
make test
# Set environment (add to .bashrc for persistence)
export VERILATOR_ROOT=$(pwd)
Optionally install GtkWave for viewing waveforms:
sudo apt install gtkwave
| Target | Command | Description |
|---|---|---|
| Qt Simulator | make qt in verilog/ |
Build for Qt desktop application |
| Calctest | make calctest in verilog/, then make in calctest/ |
Command-line test harness |
| ModelSim | make test_self in verilog/ |
CPU self-test for ModelSim |
| FPGA Hardware | make revB in verilog/ |
Assemble microcode for RevB board |
See the README files in each subfolder for detailed build instructions:
Independent research and verification projects:
| Folder | Description |
|---|---|
Pathfinding/Proto/ |
BCD arithmetic golden reference for hardware verification (submodule) |
Pathfinding/Proof/ |
Proofs of concept for complex operations using basic arithmetic |
Pathfinding/Methods/ |
C++ implementations of calculator algorithms (deprecated) |
Pathfinding/Input/ |
Numerical input state machine simulation |
Pathfinding/Mockup/ |
Keyboard layout design and user interaction testing |
This project is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
You are free to:
Under the following terms:
This is why network RFCs talk of "octets", to avoid the ambiguity. Octets are always 8 bits.
I have in my hand (I guess I like using that phase today), my father's original receipt for the HP-45 (it's with the box and manual). $299.00 in 1975, which is $1,850 today(!!!).
Relatively speaking, electronics are very, very cheap today compared to what they used to be. Still appreciate that my $30 CASIO does 90% of that the NumWorks can do, but I'm happy to support upstarts such as NumWorks.
The first book match I get for "nibble" near "byte" is in the 1964 "System 360 Assembler Language" by Don H. Stabley uses nibble. The earliest match I can find for "nybble" in relation to computers was the 1968 "Encyclopedia of library and information science". Nybble (and likely nibble) itself doesn't seem to have taken off until around the mid 1970s https://books.google.com/ngrams/graph?content=nybble&year_st...
References to the coining of the term in 1958 of course don't provide a textual source.
(* technically, a 'foot' is not a standard unit of measure but that's due to the long history of 'foot' not being standardized until relatively recently)