(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
- can I do this with a microcontroller?
- if not, how about an FPGA?
- ok, there really is no alternative to ASIC, is the market size enough to support that?With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
You can do that, but it’s going to turn out poorly.
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...
One place I worked at did fast iteration by pushing as much of the risk as they could off the silicon and by using several distinct ASICs instead of a single monolithic one which would have had better performance on its own. Gave them the ability to rev the different parts at the rate they needed it at a cost to software complexity and hardware compatibility and cost.
An SBIR is just a cost effective way for the government to put a number of PhDs/engineers to work on a problem.
If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.
But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.
Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.
The business of semiconductor design is pure intellectual property: the worlds most creative minds, building ideas that generate trillions of dollars of value. Without the minds and the ideas, the entire industry is worth almost nothing.
If this business can’t own their IP there is no business. So why would anyone build a business that gave it all away?
I sat down with Daniel Schultz, founder of aesc silicon, who’s pioneering a new semiconductor business model based on open source principles. Daniel is bootstrapping his startup. The model is not entirely new: his approach mirrors Linux’s (Red Hat) success. The core IP is free (for others), but the idea is that the value comes from support, customization, and specialized services. Revenue comes less from the product, more in the support.
Tim told us this (sorta), when we were discussing wafer.space’s success: similar to Linux, lots of users means lots of demand for improvement, and that ends up driving design and improvement faster than any traditional IP model could.
If the success of linux is any indication, this could work.
It’s early days for Daniel and the open-source silicon movement. But a customer is important for a business to survive . . . so who’s buying?
Daniel points to verifiable security as the killer app: silicon that, because it’s open source through the entire design and manufacturing supply chain, it can be verified back-door free. Chips that have auditability (you can verify nothing was slipped into your design before it hit the fab) will have an edge in cryptographic engines must be open to be trusted.
A growing source of potential customers is the increasing demand for custom chips from smaller companies. As more companies come up with more specialized chips, this has driven a benevolent cycle for fabless companies. Open source IP could drive that faster, with less time and money locked up in IP licensing.
Daniel's bet is that falling tool costs (no Cadence/Synopsys seat) plus open IP lower the barrier so far that lots of small companies start making custom chips, and that's the demand wave. The Raspberry Pi example (one engineer made their own microcontroller) is the concrete proof point.
We got a sneak preview into some open source software Daniel’s building to support this vision, IP Forge. I actually found it snooping around the aesc github account before our interview.
The concept is a package manager for open-source IP blocks. Similar to NPM or python packages (shout out to uv, my favorite python package manager!) a designer could source, compare, and download blocks of code right into their project.
I like this: IP Forge seems like a crucial tool to get customers locked in to an environment like python’s pip or uv package managers, where development speed is accelerated by rapidly building on other’s building blocks.
This, but for chip design. (https://xkcd.com/353/)
Daniel touched on one of the super powers of open-source and the tools that are growing up around it: the cheapness of experimentation. This could be the near-term factor that drives growth in the open-silicon space.
The $4-7k Wafer.Space runs let companies "try and error" instead of betting the R&D budget. We see that in Tim’s experiments, and in the Tiny-Tapeout runs: the price is low enough, engineers can take some true risks. Daniel points this out to me: there are open-source FPGAs being taped out, RISC-V processors going on wafer.space, and BlenderGDS is making chip renders that double as marketing only because the designs are open.
Inexpensive experimentation harnesses the power of biological evolution: change the design, experiment, try and die. Open source software further lowers the price.
The best part of the interview for me was talking to Daniel about why he chose to walk off on his own. He’s taking a very long view of the ecosystem, avoiding VC by choice, bootstrapped, a real legal entity, and he candidly says that "it's probably not the time to make a lot of money now, but open source will be a thing and it's fun."
I admire the long-range vision Daniel has for the ecosystem, and his courage for making a bet on himself and his vision.
More from the Siliconimist:
aesc silicon and Daniel’s projects: