Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.
It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.
I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.
Otherwise, that chip tech sounds really awesome - at least for the future!
Is there a limit to how small things can go? A single atom?
Is there a physical/molecular limit to Moore's Law?
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.
Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.
1 angstrom = 0.1 nanometers, 100 picometers
1 nanometer = 10 angstroms, 1000 picometers
1 Å = 100 pm. 1 pm = 0.01 Å.
So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.
Great to see them continuing to innovate.
But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.
Why? What's their real size?
Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.
Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)
I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
I wonder why isn't this more common.
Yes, single-atom manipulation has already been demonstrated:
* https://en.wikipedia.org/wiki/IBM_(atoms)
Can you make transistors using that technique? Can you smaller?
Currently thrown around numbers mean the "equivalent performance/density" or something like that.
You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one
Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.
The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.
However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`
(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)
[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.
Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"
I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability
We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).
Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.
Built with revolutionary “nanostack” 3D chip architecture, IBM’s sub-1 nm chip to propel semiconductor industry forward for the next decade
Jun 25, 2026

YORKTOWN HEIGHTS, NY, June 25, 2026 – IBM (NYSE: IBM) today unveiled a major semiconductor breakthrough with the introduction of the world’s first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node. The achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.
![]()
IBM’s new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM’s groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions.
Published technical results report the new chip is projected to offer a substantial leap in capability—up to 50 percent more performance, or 70 percent greater energy efficiency than IBM’s 2 nm node chips[1]—supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices.
IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.
Nanostack, an Industry Breakthrough in Chip Design
To produce this chip, IBM researchers developed an entirely new transistor architecture, called “nanostack,” the industry’s first known three-dimensional, nanosheet-based design. Nanostack represents a major advance beyond nanosheet technology, the industry’s current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other.
IBM’s nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation.
Additionally, in new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40 percent scaling in SRAM,[2] unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads.
With this groundbreaking structure, logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. With the new nanostack architecture, IBM’s semiconductor roadmap projects at least a decade of future scaling.
Building on Decades of Leadership in Semiconductor Innovation
This breakthrough is the latest testament to IBM as a leader in semiconductor R&D. IBM has led the world in developing the chips that power computing systems for decades, from early semiconductors in the 1960s to the world’s first 2 nm node chip. IBM continues to innovate at the cutting edge of silicon, AI hardware, logic, and quantum processors developed to power the future of computing.
IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra‑precise circuit printing, supporting the creation of smaller, more powerful chips. IBM and partners including Lam Research Corp. (Nasdaq: LRCX), Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd. have been working together to develop new High NA EUV processes and tools that have already yielded working devices.

IBM also recently announced a plan to form Anderon, the world’s first pure-play quantum foundry. Anderon, a standalone IBM company, will draw on IBM’s industry-leading quantum computing and semiconductor expertise to help position the United States to manufacture most of the world’s quantum wafers.
With the expectation of the earliest adoption of nanostack technology at the sub-1 nm node, IBM sees a path to production in as early as the next 5 years.
About IBM
IBM is a leading provider of global hybrid cloud and AI, and consulting expertise. We help clients in more than 175 countries capitalize on insights from their data, streamline business processes, reduce costs and gain the competitive edge in their industries. More than 4,000 government and corporate entities in critical infrastructure areas such as financial services, telecommunications and healthcare rely on IBM's hybrid cloud platform and Red Hat OpenShift to affect their digital transformations quickly, efficiently and securely. IBM's breakthrough innovations in AI, quantum computing, industry-specific cloud solutions and consulting deliver open and flexible options to our clients. All of this is backed by IBM's long-standing commitment to trust, transparency, responsibility, inclusivity and service. Visit www.ibm.com for more information.
[1] S. Reboh et al "NanoStack Transistor Architecture for CMOS 7A Node and Beyond" VLSI 2025
[2] Chen Zhang et al “Area and Performance of Staggered-Channel Nanostack SRAM Bitcells” VLSI 2026
Media contacts:
Willa Hahn
IBM Communications
willa.hahn@ibm.com
Brittany Forgione
IBM Communications
brittany.forgione@ibm.com