IBM debuts sub-1 nanometer chip technology

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible.

Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.

It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.

How does IBM commercialize this? Do they license this out to fabs?

One of the images has "15 rows of Si atoms".

Is there a limit to how small things can go? A single atom?

Is there a physical/molecular limit to Moore's Law?

> IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra‑precise circuit printing, supporting the creation of smaller, more powerful chips.

I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.

Why doesn't the industry use something like transistor density per cubic cm? This would extend to 3d cases and impossible to fake

For anyone who needs it, a friendly reminder that CPU nm marketing is a complete fabrication and the physical size of transistors has zero relation to the marketing claims. These are not, in fact, physically sub 1 nm, despite the bombastic claims.

IBM regularly announces silicon breakthroughs like this but I'm not aware of those ever becoming products. Is IBM mainly in the business of licensing their technology to big silicon manufacturers with stuff like this? Is it just marketing for their consulting business?

A little bit of a nitpick, but wouldn't that be a picometer instead of angstrom node? Like, isn't a "pico-" the next magnitude smaller than "nano-", or am i wrong?

Otherwise, that chip tech sounds really awesome - at least for the future!

Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.

It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.

As can be seen from the photos, the features are much bigger than 5 nm.

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?

> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.

yeah, where on the pictures is the 0.7nm feature? The linespacing is around 5nm. Is it the white line which is 0.7nm?

On the otherhand, no investor really cares what it's called, they just need to know it's next gen.

Why doesn't the industry use something like transistor density per cubic cm? This would extend to 3d cases and impossible to fake

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

My understanding is they are largely an IP business. That said this release mentioned an ASML machine on prem, so?

IBM's contributions to computing hardware and software are incalculable.

So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.

Great to see them continuing to innovate.

But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.

I believe that IBM makes the chips for their Z Series mainframes. I mean, that's low volume production, but they need small feature size.

>These are not, in fact, physically sub 1 nm, despite the bombastic claims.

Why? What's their real size?

Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.

The marketing nm better represent the density and performance of the transistors than the actual feature size, especially in this case.

So the title should be corrected. The did not debut sub nm chips at all.

How does IBM commercialize this? Do they license this out to fabs?

> Do they license this out to fabs?

Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.

The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.

I’m sure they will license it. It’s better for them if everyone in the industry can innovate on everything around it. All the process tech companies will make it more cost effective, for instance, which helps IBM as well.

They licensed 2 nm to Rapidus so yes.

Sit on a patent and try to scrape earnings from others, maybe? That is, license or litigate.

boost sales for their systems division, POWER CPUs, mainframes, maybe Quantum stuff

Cymer builds the EUV light source, but the biggest enabler for High NA EUV is using anamorphic optics (ie asymmetric horizontal and vertical magnification) from Zeiss: https://www.asml.com/en/news/stories/2024/5-things-high-na-e...

A little bit of a nitpick, but wouldn't that be a picometer instead of angstrom node? Like, isn't a "pico-" the next magnitude smaller than "nano-", or am i wrong?

Otherwise, that chip tech sounds really awesome - at least for the future!

One of the images has "15 rows of Si atoms".

Is there a limit to how small things can go? A single atom?

Is there a physical/molecular limit to Moore's Law?

There are 3 orders of magnitude between nano (^-9) and pico (^-12). An Angstrom is ^-10m.

Because 1 angstrom equals 10⁻¹⁰ meters and 1 picometer equals 10⁻¹² meters, the relationship is:

1 Å = 100 pm. 1 pm = 0.01 Å.

1 picometer = 0.001 nanometers, 0.01 angstrom

1 angstrom = 0.1 nanometers, 100 picometers

1 nanometer = 10 angstroms, 1000 picometers

Yes, and we're already there. We've been there for quite a while, in fact.

Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.

I mean, you can't get smaller than an atom, there is some amount of plausibility of using individual atoms as at least the occasional computing element.

Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)

As can be seen from the photos, the features are much bigger than 5 nm.

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

yeah, where on the pictures is the 0.7nm feature? The linespacing is around 5nm. Is it the white line which is 0.7nm?

I really can't see where the 0.7nm is coming from. The white line looks like it's just an edge of a feature that is "15 rows of silicon atoms", which by some quick arithmetic on Wolfram Alpha has to be AT LEAST ~1.6nm, and the way the rows of atoms appear to be packed in that image and by the provided scale, it seems to be significantly more. Using the white line as a meaningful measurement seems to me to be more misleading than any other interpretation here.

On the otherhand, no investor really cares what it's called, they just need to know it's next gen.

> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

My understanding is they are largely an IP business. That said this release mentioned an ASML machine on prem, so?

Yes, and we're already there. We've been there for quite a while, in fact.

1 picometer = 0.001 nanometers, 0.01 angstrom

1 angstrom = 0.1 nanometers, 100 picometers

1 nanometer = 10 angstroms, 1000 picometers

Because 1 angstrom equals 10⁻¹⁰ meters and 1 picometer equals 10⁻¹² meters, the relationship is:

1 Å = 100 pm. 1 pm = 0.01 Å.

You have to admit it's getting progressively sillier though.

If they're adding a dimension, the marketing should reflect that.

I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"

IBM's contributions to computing hardware and software are incalculable.

So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.

Great to see them continuing to innovate.

But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.

It's great that they found a working business model for a pure r&d lab, and with such awesome results.

I wonder why isn't this more common.

Don't forget copper interconnects for ICs. https://www.chiphistory.org/ibm-s-development-of-copper-inte...

There are 3 orders of magnitude between nano (^-9) and pico (^-12). An Angstrom is ^-10m.

The marketing nm better represent the density and performance of the transistors than the actual feature size, especially in this case.

Useless fact I just learned from Wikipedia: Ångström/Angstrom (in Sweden of course we still use the original spelling) has its own UNICODE symbol, Angstrom sign: Å (U+212B) not to confuse with the Swedish letter Å (U+00C5). Looks slightly different in my browser.

https://en.wikipedia.org/wiki/Angstrom

> https://en.wikipedia.org/wiki/There%27s_Plenty_of_Room_at_th...

Yes, single-atom manipulation has already been demonstrated:

* https://en.wikipedia.org/wiki/IBM_(atoms)

Can you make transistors using that technique? Can you smaller?

>These are not, in fact, physically sub 1 nm, despite the bombastic claims.

Why? What's their real size?

Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.

At some point in the transistor scaling, the electrons started leaking across the gate, we've switched from 2D design to 3D structures to prevent that, so the actual physical gate pitch for like the TSMC 3nm is around 45 nm in distance.

Currently thrown around numbers mean the "equivalent performance/density" or something like that.

They don't describe the exact physical size (that would rather defeat the point of the marketing), but you can see the photographs at the bottom have a scale measured in tens of nm.

I believe that IBM makes the chips for their Z Series mainframes. I mean, that's low volume production, but they need small feature size.

So the title should be corrected. The did not debut sub nm chips at all.

I mean, you can't get smaller than an atom, there is some amount of plausibility of using individual atoms as at least the occasional computing element.

Sit on a patent and try to scrape earnings from others, maybe? That is, license or litigate.

IBM Z series mainframe Telum CPUs are designed by IBM but manufactured by Samsung. IBM no longer owns any fabs. I assume they have some kind of technology licensing deal.

https://www.ibm.com/products/z/telum

That ship sailed long ago. I think it was around 32nm-22nm node when the marketing term started diverging from the physical feature size.

You could, in principle, use photons and/or electrons. We got pretty damn close in the vacuum tube era, and photonic computing has been a popular research topic for a while.

You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one

You have to admit it's getting progressively sillier though.

If they're adding a dimension, the marketing should reflect that.

I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"

Don't forget copper interconnects for ICs. https://www.chiphistory.org/ibm-s-development-of-copper-inte...

It's great that they found a working business model for a pure r&d lab, and with such awesome results.

I wonder why isn't this more common.

You had the right idea. Angstroms are not an SI unit. The SI units jump by three orders of magnitude at this scale: picometer, nanometer, micrometer, millimeter.

(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)

[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.

https://en.wikipedia.org/wiki/Angstrom

Looks like that's deprecated. From the next sentence:

However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`

They don't describe the exact physical size (that would rather defeat the point of the marketing), but you can see the photographs at the bottom have a scale measured in tens of nm.

> https://en.wikipedia.org/wiki/There%27s_Plenty_of_Room_at_th...

Yes, single-atom manipulation has already been demonstrated:

* https://en.wikipedia.org/wiki/IBM_(atoms)

Can you make transistors using that technique? Can you smaller?

That ship sailed long ago. I think it was around 32nm-22nm node when the marketing term started diverging from the physical feature size.

Currently thrown around numbers mean the "equivalent performance/density" or something like that.

You could, in principle, use photons and/or electrons. We got pretty damn close in the vacuum tube era, and photonic computing has been a popular research topic for a while.

You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one

IBM Z series mainframe Telum CPUs are designed by IBM but manufactured by Samsung. IBM no longer owns any fabs. I assume they have some kind of technology licensing deal.

https://www.ibm.com/products/z/telum

> IBM no longer owns any fabs

Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"

I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability

They licensed 2 nm to Rapidus so yes.

boost sales for their systems division, POWER CPUs, mainframes, maybe Quantum stuff

I always feel like I'm not quite getting quantum stuff no matter how much I read and learn: what does this advancement have to do with quantum computers?

> Do they license this out to fabs?

It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.

Looks like that's deprecated. From the next sentence:

However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`

You had the right idea. Angstroms are not an SI unit. The SI units jump by three orders of magnitude at this scale: picometer, nanometer, micrometer, millimeter.

(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)

[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.

Why above 1mm do we go by tens instead of thousands?

We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).

> IBM no longer owns any fabs

Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"

I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability

It's a lab. It's where ASML brings up the prototype machine and gets it working, with IBM talent working out the problems and getting it ready for commercial operation. They won't make chips at scale there: the facility isn't designed for that part.

I always feel like I'm not quite getting quantum stuff no matter how much I read and learn: what does this advancement have to do with quantum computers?

It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.

Why above 1mm do we go by tens instead of thousands?

We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).

Answer that question and you'll get the whole impetus for logarithmic scales.

>We have centimeter (10 mm) then decimeter (100mm)

Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.

Everyday necessity. The gap between mm and m is too large, there are many things in daily life that are better expressed in cm. SI units must strike a balance between three factors: not having so many denominations nobody can remember them; not having so few denominations that using them adds too much wordiness to daily life (150mm or 0.15m are wordier than 15cm); and a degree of familiarity with the everyday units people used before metric, to smooth the transition and encourage adoption.

Answer that question and you'll get the whole impetus for logarithmic scales.

>We have centimeter (10 mm) then decimeter (100mm)

Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.

Built with revolutionary “nanostack” 3D chip architecture, IBM’s sub-1 nm chip to propel semiconductor industry forward for the next decade

Jun 25, 2026

YORKTOWN HEIGHTS, NY, June 25, 2026 – IBM (NYSE: IBM) today unveiled a major semiconductor breakthrough with the introduction of the world’s first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node. The achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

IBM’s new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM’s groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions.

Published technical results report the new chip is projected to offer a substantial leap in capability—up to 50 percent more performance, or 70 percent greater energy efficiency than IBM’s 2 nm node chips[1]—supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices.

IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.

Nanostack, an Industry Breakthrough in Chip Design

To produce this chip, IBM researchers developed an entirely new transistor architecture, called “nanostack,” the industry’s first known three-dimensional, nanosheet-based design. Nanostack represents a major advance beyond nanosheet technology, the industry’s current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other.

IBM’s nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation.

Additionally, in new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40 percent scaling in SRAM,[2] unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads.

With this groundbreaking structure, logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. With the new nanostack architecture, IBM’s semiconductor roadmap projects at least a decade of future scaling.

Building on Decades of Leadership in Semiconductor Innovation

This breakthrough is the latest testament to IBM as a leader in semiconductor R&D. IBM has led the world in developing the chips that power computing systems for decades, from early semiconductors in the 1960s to the world’s first 2 nm node chip. IBM continues to innovate at the cutting edge of silicon, AI hardware, logic, and quantum processors developed to power the future of computing.

IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra‑precise circuit printing, supporting the creation of smaller, more powerful chips. IBM and partners including Lam Research Corp. (Nasdaq: LRCX), Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd. have been working together to develop new High NA EUV processes and tools that have already yielded working devices.

IBM also recently announced a plan to form Anderon, the world’s first pure-play quantum foundry. Anderon, a standalone IBM company, will draw on IBM’s industry-leading quantum computing and semiconductor expertise to help position the United States to manufacture most of the world’s quantum wafers.

With the expectation of the earliest adoption of nanostack technology at the sub-1 nm node, IBM sees a path to production in as early as the next 5 years.

About IBM

IBM is a leading provider of global hybrid cloud and AI, and consulting expertise. We help clients in more than 175 countries capitalize on insights from their data, streamline business processes, reduce costs and gain the competitive edge in their industries. More than 4,000 government and corporate entities in critical infrastructure areas such as financial services, telecommunications and healthcare rely on IBM's hybrid cloud platform and Red Hat OpenShift to affect their digital transformations quickly, efficiently and securely. IBM's breakthrough innovations in AI, quantum computing, industry-specific cloud solutions and consulting deliver open and flexible options to our clients. All of this is backed by IBM's long-standing commitment to trust, transparency, responsibility, inclusivity and service. Visit www.ibm.com for more information.

[1] S. Reboh et al "NanoStack Transistor Architecture for CMOS 7A Node and Beyond" VLSI 2025

[2] Chen Zhang et al “Area and Performance of Staggered-Channel Nanostack SRAM Bitcells” VLSI 2026

Media contacts:

Willa Hahn
IBM Communications
willa.hahn@ibm.com

Brittany Forgione
IBM Communications
brittany.forgione@ibm.com

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IBM debuts sub-1 nanometer chip technology

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