Even more interesting that they both use the IBM POWER architecture!
0, https://www.moog.com/products/avionics/spacecraft-avionics/b...
1, https://en.wikipedia.org/wiki/RAD5500
2, https://web.archive.org/web/20190226111129/https://www.baesy...
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
I seriously doubt you need to fabricate 50k CPUs for a single space probe, including backups, testing chips, etc.
> An 8085 processor that could handle 1×106 rads of radiation with only a 25% reduction in performance, and 3×106 rads with a 40% drop.
Hmm, from where did they copy-paste this mangled scientific notation?
Ah here we are, pg. 37 (46 in PDF file): https://apps.dtic.mil/sti/tr/pdf/ADA063902.pdf
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
In comparison radtherapy patients get 20 gray in 1-2 weeks so it's the 20/10000 = 0.02% of what these designs target
What, so that they can debug in Chrome and put the fusing and inertial navigation processes in isolated web views?
The customer would order this minimum quantity, and most of it will probably be kept as spares.
"The Beginning - In July of 1951, Bill Moog, Art Moog, and Lou Geyer pooled $3,000 and opened Moog Valve. They had limited resources..."
vs "The Moog synthesizer (/moʊɡ/ MOHG) is a modular synthesizer invented by the American engineer Robert Moog in 1964. Moog's company, R. A. Moog Co., produced numerous..."The inertial navigation system is the very crazy part, along with the nuclear fusion warhead design itself.
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
Back then an interface between terrestrial computer systems and a Zeta Reticulan spacecraft required a small supercomputer on our side.
https://thebulletin.org/2017/03/how-us-nuclear-force-moderni...
We need more of this kind of thing, generally: government agencies building up in-house technical capability, instead of outsourcing everything to contractors.
For instance: there should be a government-controlled pharmaceutical manufacturer of last resort. The clear benefits would be to provide extra capacity and prevent things like Martin Shkreli's scams with Retrophin/Turing Pharmaceuticals (https://en.wikipedia.org/wiki/Martin_Shkreli#Thiola_price_hi...).
But then how will politicians favor their campaign donors?
Back in the late 1970’s and early 1980’s Sandia National Laboratory (in Albuquerque NM USA) began building the capacity to design, fab, and test IC’s at scale (packaging was handled by Fairchild and Allied Signal). Why would a National Laboratory need the capacity to do this? To provide components that were not available commercially. In this case, Sandia’s goal was to make radiation hardened devices for use in weapons and space missions. The harshest environments and where reliability was paramount.
Sandia began their fab in 1978 on 2″ wafers on a 10u process, a few generations behind ‘state of the art’. By 1982 this was upgraded to a 4″ wafer system with features as small as 2u. This was the design node that Sandia used to make all the IC’s used in the Galileo space probe (for its mission to Jupiter). This included the 1802 processor from RCA. Sandia received the logic diagrams of the processor and its support chips and recreated them in a radiation hardened process. How many IC’s were needed? Over 50,000 for the probe itself, backups, testing chips etc.
Sandia also produced various IC’s for weapons’ systems, and not things like tanks or planes or ships, but weapons that need IC’s that can handle intense radiation, these were generally nuclear warheads, reentry vehicles, ICBMs and things along those lines. Sandia made the chips for them, as well as maintains a ‘war reserve’ stock of replacement ICs for when they are needed.
In 1982 Sandia began work on a CMOS rad-hard conversion of the Intel 8085 processor. This would become the Sandia SA3000. Converting the HMOS Intel 8085 to a rad hard CMOS process took some doing. The original 8085 had around 6500 transistors. Converting it to CMOS resulted in a 18,000 transistor device. One of the trickier conversions was the instruction decoder (a large PLA), easy in NMOS, less so in CMOS. The SA3000 was made on 4″ wafers on a 3u process.
Sandia SA3000 – Lot G Wafer 18 – Made in 1984
Die size was 228-239 mils and it operated at 4.5-11V, while maintaining compatibility at 5V for testing. The increased voltage gives a lot more ‘head room’ for radiation effects, as radiation exposure tends to slow the max device speed down. Sandia also made a set of support chips for the SA3000, the SA3001 (Intel 8155), the SA3002 (Intel 8355), SA3026 (Intel 8212) and many others as needed.
SA3001 – Intel 8155
Designing for radiation hardness is an art and a science, much went into the design to make it work reliably. The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides (largely a process of controlling production temps). Contact of power to the substrate and ground to the guardband and p-well is made as often as possible to further aid in latchup control.
What did this get Sandia? An 8085 processor that could handle 1×106 rads of radiation with only a 25% reduction in performance, and 3×106 rads with a 40% drop. The design goal was 1×105 so they greatly exceeded that. Anything over 1000 rads in generally fatal for humans.
The SA3000 was used (and still is) in the W88 475kt nuclear warhead used on the Submarine launched Trident II. It runs the main computer/programmer responsible for altitude and fuzing calculations. The SA3000 was also used by Ball aerospace for a deep space star tracker design and used on the Combined Release and Radiation Effects Satellite (CRRES) in 1990 to study the effects of high radiation on electronics. The electronics on the CRRES worked fine, but the battery failed after only a year causing an early mission failure.
In around 1984-1985 the govt decided to bring in a contractor to run the fab much to the annoyance of Sandia management and detriment to efficiency. This would be Allied Signal, who at that point had no experience running fab’s. This greatly slowed down production for some time.
Harris HS1-80C85RH-Q
Serial # 0001
The SA3000 (and its support chips) were commercialized by Harris in 1990 as the HS1-80C85RH and the HS9-80C85RH. These are similar to the SA3000, made on the same process, but spec’d with only a 5V operating voltage rather than 10V and a max speed of 2MHz rather then the 10MHz the SA3000 is capable of. The HS1 is space grade, with higher levels of screening, and the HS9 is military grade, but not screened to space use levels.