Mythic's analog compute-in-memory architecture

My understanding (perhaps outdated) is that manufacturing variability is a key challenge for analog computing. Digital designs are also fundamentally analogue under the hood, but if you only need to resolve a 0 or 1 you are much more tolerant of any source of noise. I wouldn't mind hearing even a little bit more from Mythic about how they make this work in practice.

A 2026 EE Times article [1] refers to "compensation" and "calibration" techniques.

[1] https://www.eetimes.com/mythic-rises-from-the-ashes-with-125...

If you’re looking for their LLM page it’s https://www.mythic.ai/enterprise-llm

I wish they would have done what Taalas did with chatjimmy.ai and just directly host a model for us to view, rather than just claiming it’s 50x faster than Nvidia/groq. Their claim is specifically for a 1 trillion param model. So they could have just grabbed GLM 5.2, or similar, and hosted it.

> Mythic M1 stores up to 80 million neural network weight parameters directly on-chip

Which means connecting ~350 chiplets to run a Qwen 3.8 27b and over 30000 chiplets to run Qwen3.8-2.4T-A95B. Cost? Space? Feasibility?

Edit: wrong values, lost a zero...

Edit: seemingly, the M1 is only part of the whole need. With the M1, you would run a feedforward pass of the NN but use the rest of the Von Neumann architecture to manage the data. The pass in the M1 will be lightning fast, the rest still a bottleneck. The M1 is almost explicitly not for LLMs.

Their numbers look too good to be true, they have no identified customers and the whole site is generated, but I think the principle behind it is good. If they can pull off the error correction needed to make analog reliable we might have a great new option for cheaper more eco friendly AI. Then again it could turn out to be a total scam.

This looks cool a chiplet can fit 30m params so the biggest card can fit qwen 3.8 27b it would be cool to see some benchmarks on things like that publically.

So much work is being done on running these things more efficiently, and it’s why I think the data center build out is a huge bubble.

A 2026 EE Times article [1] refers to "compensation" and "calibration" techniques.

[1] https://www.eetimes.com/mythic-rises-from-the-ashes-with-125...

If you go for a full curve over the space, then yes.

But like NAND, there is room for, I don’t know what to call it, “quantization”? You get a few values out instead of just binary.

My guess is, like other issues of precision, errors can get out of hand if you are not careful.

But being an EE in another life, I can tell you the power waste and slowness of ALUs is kinda wild.

I definitely believe that Gaming on CPUs is like ML on GPUs. Slow, and waiting for something more appropriate to come along.

Don’t know if these guys are the ones to do it (and they are, ahem, not alone). But someone will deliver 100x to 1000x boost either in speed, power efficiency, or both.

You reminded me the anecdote about every SID chip sounding different. If you hear a recording of a C64 made song, it’s unique to that chip (and somewhat to the machine as well, timing, crystal, etc.).

I'd assume it does some type of calibrate per device (regularly?) or the design is such that it's differential so things cancel out. Note it's also on 28nm for the analogue bits because yes it's harder.

Since no sane person expects reliable results from these chatbots, unreliable analog implementations should be fine.